Minimum-Perturbation Retiming for Delay Optimization

This paper describes a fast retiming algorithm targeting delay while minimizing the number of flip-flops moved. The algorithm can be applied before placement to minimize logic level, or after placement to minimize the critical region annotated with wire delays. Experiments on a suite of industrial benchmarks show that the algorithm improves fMAX by 9% while increasing LUT count by 1% and flip-flop count by 2%, respectively. The runtime penalty is less than 1% of the total runtime of the design flow.